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Noise optimization of an inductively degenerated CMOS low noise amplifier

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Author

Summary, in English

This paper presents a technique for substantially reducing the noise of a CMOS low noise amplifier implemented in the inductive source degeneration topology. The effects of the gate induced current noise on the noise performance are taken into account, and the total output noise is strongly reduced by inserting a capacitance of appropriate value in parallel with the amplifying MOS transistor of the LNA. As a result, very low noise figures become possible already at very low power consumption levels

Publishing year

2001

Language

English

Pages

835-841

Publication/Series

IEEE Transactions on Circuits and Systems - 2, Analog and Digital Signal Processing

Volume

48

Issue

9

Document type

Journal article

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Status

Published

ISBN/ISSN/Other

  • ISSN: 1057-7130