A CMOS implementation of a video-rate successive approximation A/D converter

Summary, in English

Previous approaches to video-rate CMOS A/D (analog-to-digital) converters are based on fully-parallel, subrange, or pipeline architectures. The authors describe a 5-MHz 8-bit experimental design of a successive-approximation A/D converter using 3-μm CMOS technology. Since neither capacitors nor a resistor string are needed in the current-switching technique, a conventional digital technology can be used. The use of the CMOS current-switch technique makes bipolar input signals possible. A circuit realization of a high-speed successive approximation register is also presented, using a single phase clock. The proposed technique is compatible with digital VLSI technology.

• Author: Keping Chen; Christer Svensson; Jiren Yuan
• Publishing year: 1988
• Language: English
• Pages: 2577-2580
• Publication/Series: [Host publication title missing]
• Volume: 3
• Links: http://dx.doi.org/10.1109/ISCAS.1988.15468
• Document type: Conference paper
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: IEEE International Symposium on Circuits and Systems, 1988
• Conference date: 1988-06-07 - 1988-06-09
• Conference place: Espoo, Finland
• Status: Published