A PLL based 12 GHz LO generator with digital phase control in 90 nm CMOS

Summary, in English

A 12 GHz PLL with digital output phase control has been implemented in a 90 nm CMOS process. It is intended for LO signal generation in integrated phased array transceivers. Locally placed PLLs eliminate the need of long high frequency LO routing to each transceiver in a phased array circuit. Routing losses are thereby reduced and the design of integrated phased array transceivers becomes more modular. A chip was manufactured, featuring two separate fully integrated PLLs operating at 12 GHz, with a common 1.5 GHz reference. The chip, including pads, measures 1050 × 700 μm2. Each PLL consumes 15 mA from a 1.2 V supply, with a typical measured phase noise of −110 dBc/Hz at 1 MHz offset. The phase control range exceeds 360°.

• Author: Andreas Axholt; Henrik Sjöland
• Department/s: Department of Electrical and Information Technology; ELLIIT: the Linköping-Lund initiative on IT and mobile communication
• Publishing year: 2011
• Language: English
• Pages: 309-318
• Publication/Series: Analog Integrated Circuits and Signal Processing
• Volume: 67
• Issue: 3
• Links: http://dx.doi.org/10.1007/s10470-011-9619-4
• Document type: Journal article
• Publisher: Springer
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Status: Published
• Project: EIT_HSWC:RFNano RF tranceivers and nano devices
• Research group: Elektronikkonstruktion; Analog RF
• ISBN/ISSN/Other: ISSN: 0925-1030