An Analog (7,5) Convolutional Decoder in 65 nm CMOS for Low Power Wireless Applications
Author
Summary, in English
presented for a low power analog convolutional decoder in 65 nm CMOS.
The decoder core operates in the weak inversion (sub-VT) and realizes the
BCJR decoding algorithm corresponding to the 4-state tail-biting trellis of
a (7,5) convolutional code. The complete decoder also incorporates serial
I/O digital interfaces and current mode differential DACs. The simulated
bit error rate is presented to illustrate the coding gain compared to an
uncoded system. Our results show that a low power, high throughput
convolutional decoder up to 1.25 Mb/s can be implemented using analog
circuitry with a total power consumption of 84 μW. For low rate
applications the decoder consumes only 47 μW at a throughput of 250
kb/s.
Department/s
Publishing year
2011
Language
English
Pages
2881-2884
Publication/Series
[Host publication title missing]
Document type
Conference paper
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
Conference name
IEEE International Symposium on Circuits and Systems (ISCAS 2011), 2011
Conference date
2011-05-15 - 2011-05-18
Conference place
Rio de Janeiro, Brazil
Status
Published
Research group
- Analog RF
- Digital ASIC
- Telecommunication Theory
ISBN/ISSN/Other
- ISSN: 0271-4310
- ISSN: 2158-1525
- ISBN: 978-1-4244-9473-6