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Power Constrained Test Scheduling for 3D Stacked Chips: poster

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Author

Publishing year

2010

Language

English

Document type

Poster

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits

Conference date

2010-11-04 - 2010-11-05

Conference place

Austin, United States

Status

Published

Research group

  • Digital ASIC