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A hardware efficiency analysis for simplified trellis decoding blocks

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Author

Summary, in English

Two simplifications for trellis decoding blocks are analyzed in terms of hardware efficiency. Both architectures use a complementary property of the best rate 1/n convolutional codes to reduce arithmetic complexity. While the reduction can be calculated straightforward in the first approach (17%), the other approach relies on modified computational operations and hence this reduction is not as evident. It is shown that for rate 1/2 codes the first approach is preferable for hardware implementation in terms of area and speed.

Publishing year

2005

Language

English

Pages

128-132

Publication/Series

[Host publication title missing]

Volume

2005

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Trellis decoding blocks
  • Computational operations
  • Hardware efficiency

Conference name

IEEE Workshop on Signal Processing Systems - Design and Implementation (SiPS)

Conference date

2005-11-02 - 2005-11-04

Conference place

Athens, Greece

Status

Published

ISBN/ISSN/Other

  • ISSN: 1520-6130
  • ISBN: 0-7803-9333-3