Coprocessor accelerated OpenMAX MP3 decoder
Author
Summary, in English
This thesis evaluates the feasibility of designing a coprocessor to
accelerate multimedia functions in the OpenMAX standard. OpenMAX is a new standard from the Khronos group, a member funded industry consortium, to integrate the most popular multimedia functions like MP3, MPEG-4 and H.264 under one roof. It provides royalty-free API that helps in developing and/or
accelerating the specified standards on a wide variety of platforms and devices. The MP3 subsection in OpenMAX was implemented for evaluating the standard. A high level simulation model of the system consists of a processor core, cache, memory and coprocessor. The coprocessor provides
instruction set extensions for the CPU to accelerate the intended functions and was modeled using SystemC like language. The result is evaluated in terms of the speedup obtained. The MP3 decoding process was accelerated 1.2 times as a result of accelerating the DCT by 4 times. The simulations further established the importance of avoiding memory access bottlenecks. The silicon area of the coprocessor was estimated to be half of the original specification limit.
accelerate multimedia functions in the OpenMAX standard. OpenMAX is a new standard from the Khronos group, a member funded industry consortium, to integrate the most popular multimedia functions like MP3, MPEG-4 and H.264 under one roof. It provides royalty-free API that helps in developing and/or
accelerating the specified standards on a wide variety of platforms and devices. The MP3 subsection in OpenMAX was implemented for evaluating the standard. A high level simulation model of the system consists of a processor core, cache, memory and coprocessor. The coprocessor provides
instruction set extensions for the CPU to accelerate the intended functions and was modeled using SystemC like language. The result is evaluated in terms of the speedup obtained. The MP3 decoding process was accelerated 1.2 times as a result of accelerating the DCT by 4 times. The simulations further established the importance of avoiding memory access bottlenecks. The silicon area of the coprocessor was estimated to be half of the original specification limit.
Publishing year
2006
Language
English
Document type
Report
Publisher
[Publisher information missing]
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
Status
Published