The browser you are using is not supported by this website. All versions of Internet Explorer are no longer supported, either by us or Microsoft (read more here: https://www.microsoft.com/en-us/microsoft-365/windows/end-of-ie-support).

Please use a modern browser to fully experience our website, such as the newest versions of Edge, Chrome, Firefox or Safari etc.

Defect-Aware SOC Test Scheduling

På svenska

Author

Summary, in English

In this paper we address the test scheduling problem for system-on-chip designs. Different from previous approaches where it is assumed that all tests will be performed until completion, we consider the cases where the test process will be terminated as soon as a defect is detected. This is common practice in production test of chips. The proposed technique takes into account the probability of defect-detection by a test in order to schedule the tests so that the expected total test time will be minimized. We investigate different test bus structures, test scheduling strategies (sequential scheduling vs. Concurrent scheduling), and test set assumptions (fixed test time vs. Flexible test time). We have also made experiments to illustrate the efficiency of taking defect probability into account during test scheduling.

Publishing year

2004

Language

English

Pages

359-364

Publication/Series

VLSI Test Symposium, 2004. Proceedings. 22nd IEEE

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • system-on-chip
  • defect-detection
  • test scheduling
  • sequential scheduling
  • concurrent scheduling
  • defect probabilities

Conference name

2004 IEEE VLSI Test Symposium VTS04

Conference date

0001-01-02

Status

Published

ISBN/ISSN/Other

  • ISSN: 1093-0167
  • ISBN: 0-7695-2134-7