The browser you are using is not supported by this website. All versions of Internet Explorer are no longer supported, either by us or Microsoft (read more here: https://www.microsoft.com/en-us/microsoft-365/windows/end-of-ie-support).

Please use a modern browser to fully experience our website, such as the newest versions of Edge, Chrome, Firefox or Safari etc.

Design of RF Properties for Vertical Nanowire MOSFETs

På svenska

Author

Summary, in English

The RF performance of vertical nanowire metal-oxide-semiconductor field-effect transistors in realistic layouts has been calculated. The parasitic capacitances have been evaluated using full 3-D finite-element method calculations, combined with self-consistent Schrodinger-Poisson calculations for the intrinsic gate capacitances. It is shown that a performance comparable to planar FETs can be achieved in the vertical geometry by scaling the nanowire diameter and the wire-to-wire separation.

Publishing year

2011

Language

English

Pages

668-673

Publication/Series

IEEE Transactions on Nanotechnology

Volume

10

Issue

4

Document type

Journal article

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Condensed Matter Physics
  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Field-effect transistors
  • InAs
  • metal-oxide-semiconductor field-effect
  • transistor (MOSFET)
  • modeling
  • nanowire
  • parasitic capacitance

Status

Published

Research group

  • Nano

ISBN/ISSN/Other

  • ISSN: 1536-125X