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Optimal System-on-Chip Test Scheduling

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Author

Summary, in English

In this paper, we show that the scheduling of tests on the test access mechanism (TAM) is equivalent to independent job scheduling on identical machines and we make use of an existing preemptive scheduling algorithm to produce an optimal solution in linear time. We extend the algorithm to handle (1) test conflicts due to interconnection tests and (2) cases when a test limits an optimal usage of the TAM by using reconfigurable core test wrappers. Our extensions preserve the production of an optimal solution in respect to test time and minimizes the number of wrapper configurations as well as the TAM usage at each core, which implicitly minimizes the TAM routing. Experiments with our implementation shows its efficiency in comparison with previous approaches.

Publishing year

2003

Language

English

Pages

306-311

Publication/Series

[Host publication title missing]

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • test scheduling
  • test access mechanisms
  • TAM
  • test conflicts
  • test wrappers
  • TAM routing

Conference name

12th IEEE Asian Test Symposium ATS03

Conference date

2003-11-16 - 2003-11-19

Conference place

Xi'an, China

Status

Published

ISBN/ISSN/Other

  • ISSN: 1081-7735
  • ISBN: 0-7695-1951-2