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Efficient CMOS counter circuits

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Author

  • Jiren Yuan

Summary, in English

Several efficient counters are presented. A nine-transistor divide-by-two circuit is used as a basic building block. With transistor sizing, an input frequency of 400 MHz can be adopted by an asynchronous counter, while an eight-bit synchronous counter can achieve clock rates of more than 200 MHz in a 3-μm CMOS process. The power consumption of the proposed precharged dynamic synchronous counter is reduced to almost half as much as normal

Publishing year

1988

Language

English

Pages

1311-1313

Publication/Series

Electronics Letters

Volume

24

Issue

21

Document type

Journal article

Publisher

IEE

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Status

Published

ISBN/ISSN/Other

  • ISSN: 1350-911X