The browser you are using is not supported by this website. All versions of Internet Explorer are no longer supported, either by us or Microsoft (read more here: https://www.microsoft.com/en-us/microsoft-365/windows/end-of-ie-support).

Please use a modern browser to fully experience our website, such as the newest versions of Edge, Chrome, Firefox or Safari etc.

Development of a Vertical Wrap-Gated InAs FET

På svenska

Author

  • Claes Thelander
  • Carl Rehnstedt
  • Linus E. Froberg
  • Erik Lind
  • Thomas Martensson
  • Philippe Caroff
  • Truls Lowgren
  • B. Jonas Ohlsson
  • Lars Samuelson
  • Lars-Erik Wernersson

Summary, in English

In this paper, we report on the development of a vertical wrap-gated field-effect transistor based on epitaxially grown InAs nanowires. We discuss some of the important steps involved in the growth and processing, such as nanowire position control in situ doping, high-kappa dielectric deposition, spacer layer formation: and metal wrap-gate fabrication. In particular, we compare a few alternative methods for deposition of materials onto vertical structures and discuss their potential advantages and limitations. Finally, we also present a comparison of transistor performance for nanowires grown using two different epitaxial techniques.

Publishing year

2008

Language

English

Pages

3030-3036

Publication/Series

IEEE Transactions on Electron Devices

Volume

55

Issue

11

Document type

Journal article

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Condensed Matter Physics
  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • nanowire
  • Field-effect transistor (FET)
  • InAs
  • wrap gate
  • surround gate

Status

Published

Research group

  • Nano

ISBN/ISSN/Other

  • ISSN: 0018-9383