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Power Efficient Redundant Execution for Chip Multiprocessors

Author

  • Pramod Subramanyan
  • Virendra Singh
  • Kewal K. Saluja
  • Erik Larsson

Summary, in English

This paper describes the design of a power efficient microarchitecture for transient fault detection in chip multiprocessors (CMPs) We introduce a new per-core dynamic voltage and frequency scaling (DVFS) algorithm for our architecture that significantly reduces power dissipation for redundant execution with a minimal performance overhead. Using cycle accurate simulation combined with a simple first order power model, we estimate that our architecture reduces dynamic power dissipation in the redundant core by an mean value of 79% and a maximum of 85% with an associated mean performance overhead of only 1.2%.

Publishing year

2009

Language

English

Pages

1-6

Document type

Conference paper

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

Workshop on Dependable and Secure Nanocomputing

Conference date

2009-06-29

Conference place

Lisbon, Portugal

Status

Published