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A 3.6mW, 90nm CMOS Gated-Vernier Time-to-Digital Converter with an Equivalent Resolution of 3.2ps

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Author

Summary, in English

Two gated ring oscillators (GROs) act as the delay lines in an improved Vernier time-to-digital converter (TDC), where the already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. The TDC has been implemented in a 90nm CMOS process and consumes 3mA from 1.2V when operating at 25MHz. The native Vernier resolution of the TDC is 5.8ps, while the total noise integrated over a bandwidth of 800kHz yields an equivalent TDC resolution of 3.2ps.

Publishing year

2012

Language

English

Pages

1626-1635

Publication/Series

IEEE Journal of Solid-State Circuits

Volume

47

Issue

7

Document type

Journal article

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Gated Ring Oscillator
  • Time-to-Digital Converter
  • Vernier Delay Line

Status

Published

ISBN/ISSN/Other

  • ISSN: 0018-9200