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A 90nm CMOS Gated-Ring-Oscillator-Based Vernier Time-to-Digital Converter with Improved Resolution

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Author

Summary, in English

Two gated ring oscillators (GRO) act as the delay lines in an improved Vernier time-to-digital converter (TDC). The already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. The TDC has been implemented in a 90nm CMOS technology and achieves a resolution better than 5ps for a signal bandwidth of 800kHz. The current consumption is 3mA from 1.2V when operating at 25MHz.

Publishing year

2011

Language

English

Pages

459-462

Publication/Series

[Host publication title missing]

Document type

Conference paper

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Time-to-Digital Converter
  • Gated Ring Oscillator
  • Vernier Delay Line

Conference name

IEEE European Solid State Circuits Conference, ESSCIRC 2011

Conference date

2011-09-12 - 2011-09-16

Conference place

Helsinki, Finland

Status

Published

ISBN/ISSN/Other

  • ISSN: 1930-8833
  • ISBN: 978-1-4577-0703-2