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An OFDM Timing Synchronization ASIC

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Author

Summary, in English

In this paper an OFDM timing synchronization ASIC is presented. The proposed synchronization unit can be used in any OFDM system. The algorithm is based on the correlation introduced by the cyclic prefix, which is exploited in the time domain where the time offset is estimated. Although the algorithm is too complex to be implemented on today's most powerful standard DSP, a hardware architecture that is optimized for the algorithm is implemented with moderate complexity. The unit contains 32 kbit RAM and 3000 gates. At the sample rate of 25 Msamples/s the power consumption is 16 mW, which is small for such a complex algorithm

Publishing year

2000

Language

English

Pages

324-327

Publication/Series

The 7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000.

Volume

1

Document type

Conference paper

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

7th IEEE International Conference on Electronics, Circuits and Systems (ICECS’2K)

Conference date

2000-12-14 - 2000-12-17

Conference place

Kaslik, Lebanon

Status

Published

Research group

  • Elektronikkonstruktion

ISBN/ISSN/Other

  • ISBN: 0-7803-6542-9