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A Programmable 10b up-to-6MS/s SAR-ADC Featuring Constant-FoM with On-Chip Reference Voltage Buffers

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Author

  • F. Borghetti
  • J. Nielsen
  • V. Ferragina
  • P. Malcovati
  • Pietro Andreani
  • A. Baschirotto

Summary, in English

A 10bit SAR-ADC implemented in a 1.2V 0.13mum CMOS with 1VppdiffFS, based on capacitive-charge redistribution can be programmed with Fs up-to-6MS/s, guaranteeing an ENOB>9b with a SFDR>74dB. The static INL and DNL are 0.6LSB and 0.55LSB, respectively. On-chip reference buffer have been added and their power consumption dominates, giving a FoMap1pJ/conv. Sharing these buffers with other blocks in SoC structure, reduces the ADC power consumption to 200muW and the FoMap0.1pJ/conv. This appears an attractive solution for embedded ADC

Publishing year

2006

Language

English

Pages

500-503

Publication/Series

Proceedings of the 32nd European Solid-State Circuits Conference, 2006. ESSCIRC 2006.

Document type

Conference paper

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Status

Published

ISBN/ISSN/Other

  • ISSN: 1930-8833
  • ISBN: 1-4244-0303-0