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Scheduling Tests for 3D Stacked Chips under Power Constraints

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Author

Summary, in English

This paper addresses Test Application Time (TAT)reduction for core-based 3D Stacked ICs (SICs). Applyingtraditional test scheduling methods used for non-stacked chiptesting where the same test schedule is applied both at wafer testand at final test to SICs, leads to unnecessarily high TAT. This isbecause the final test of 3D-SICs includes the testing of all thestacked chips. A key challenge in 3D-SIC testing is to reduce TATby co-optimizing the wafer test and the final test while meetingpower constraints. We consider a system of chips with coresequipped with dedicated Built-In-Self-Test (BIST)-engines andpropose a test scheduling approach to reduce TAT while meetingthe power constraints. Depending on the test schedule, the controllines that are required for BIST can be shared among severalBIST engines. This is taken into account in the test schedulingapproach and experiments show significant savings in TAT.

Publishing year

2011

Language

English

Pages

72-77

Publication/Series

2011 Sixth IEEE International Symposium on Electronic Design, Test and Application

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Design for Test (DfT)
  • Built in Self Test (BIST)
  • Test scheduling
  • Sessions
  • Test time
  • Test cost
  • 3D Stacked Integrated Circuit (SIC)
  • Through Silicon Via (TSV).

Conference name

6th International Symposium on Electronic Design, Test and Applications (DELTA 2011)

Conference date

0001-01-02

Conference place

Queenstown, New Zealand

Status

Published

Research group

  • Digital ASIC

ISBN/ISSN/Other

  • ISBN: 978-1-4244-9357-9