Globally Asynchronous Locally Synchronous Architecture for Large High-performance ASICs

Summary, in English

Clock nets are the major source of power consumption in large, high-performance ASICs and a design bottleneck when it comes to tolerable clock skew. A way to obviate the global clock net is to partition the design into large synchronous blocks each having its own clock. Data with other blocks is exchanged asynchronously using handshake signals. Adopting such a strategy requires a methodology that supports: 1) a partitioning method dividing a design into the number of synchronous blocks such that the gain due to global clock net removal exceeds the communication overhead and 2) synthesis of handshake protocols to implement the data transfer between synchronous blocks. We describe this methodology and present results of applying it to a realistic design done in 0.25 micron, ranging in operating frequencies from 20 MHz to 1 GHz. The results show that the net power savings compared to fully synchronous designs are on an average about 30%

• Author: Thomas Meincke; Ahmed Hemani; Shashi Kumar; Johnny Öberg; Thomas Olsson; Peter Nilsson; Dan Lindqvist; Hannu Tenhunen
• Department/s: Departments at LTH; Department of Electrical and Information Technology
• Publishing year: 1999
• Language: English
• Pages: 512-515
• Publication/Series: Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99.
• Volume: 2
• Links: http://dx.doi.org/10.1109/ISCAS.1999.780794
• Document type: Conference paper
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: 1999 International Symposium on Circuits and Systems (ISCAS’99)
• Conference date: 1999-05-30 - 1999-06-02
• Conference place: Orlando, Florida, United States
• Status: Published
• Research group: Elektronikkonstruktion
• ISBN/ISSN/Other: ISBN: 0-7803-5471-0