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Power reductions in unrolled CORDIC architectures

På svenska

Author

  • Peter Nilsson
  • Syed Nadeemuddin

Summary, in English

This paper shows a novel methodology to reduce the power consumption and complexity in unrolled CORDIC architectures. It is a methodology is based on removing adder and subtractor stages starting from the first stage. The stages are replaced with a number of MUXes. Three to four stages can be removed with substantial reduction in complexity and power consumption. The methodology is applicable on CORDICs with an arbitrary number of stages. Here, a six stage CORDIC is used as an example to show the methodology. The paper shows that the complexity can be decreased by 29 % and the dynamic power consumption can be reduced by 59 %

Publishing year

2011

Language

Swedish

Document type

Conference paper

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

European Conference on Circuit Theory and Design (ECCTD 2011)

Conference date

2011-08-29

Conference place

Linköping, Sweden

Status

Published

Research group

  • Digital ASIC