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A 10-bit 500-MS/s 124-mW subranging folding ADC in 0.13 μm CMOS

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Author

  • Cheng Chen
  • Jiren Yuan

Summary, in English

A 10-bit two-step subranging folding analog-to-digital converter (ADC) that converts signal at 500 MSample/s is presented. Using dual-channel preprocessing blocks with distributed sample-and-hold circuits and two-stage amplifiers in which auto-zero calibration technique is employed, the proposed 10-bit ADC has a wide input bandwidth (>250MHz). The ADC consumes 124mW from a 1.2V power supply. The performance is verified by Sepctre simulation in a digital 0.13μm CMOS process. The chip occupies an active area of 0.54mm<sup>2</sup>. © 2007 IEEE.

Publishing year

2007

Language

English

Pages

1709-1712

Publication/Series

Proceedings - IEEE International Symposium on Circuits and Systems

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Preprocessing blocks
  • Auto-zero calibration
  • Wide input bandwidth
  • Sepctre simulation

Conference name

2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007

Conference date

2007-05-27 - 2007-05-30

Conference place

New Orleans, LA, United States

Status

Published

ISBN/ISSN/Other

  • ISSN: 2158-1525
  • ISSN: 0271-4310
  • CODEN: PICSDI