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Test Time Analysis for IEEE P1687

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Author

  • Farrokh Ghani Zadegan
  • Urban Ingelsson
  • Gunnar Carlsson
  • Erik Larsson

Summary, in English

The IEEE P1687 (IJTAG) standard proposal aims at providing a standardized interface between on-chip embedded logic (instruments), such as scan-chains and temperature sensors, and the IEEE 1149.1 standard which provides test data transport and test protocol for board test. A key feature in P1687 is to include Select Instrument Bits (SIBs) in the scan path to allow flexibility in test architecture design and test scheduling. This paper presents algorithms to compute the test time in a P1687 context. The algorithms are based on analysis for flat and hierarchical test architectures, considering two test schedule types - concurrent and sequential test scheduling. Furthermore, two types of overhead are identified, i.e. control data overhead and JTAG protocol overhead. The algorithms are implemented and employed in experiments on realistic industrial designs.

Publishing year

2010

Language

English

Pages

455-460

Publication/Series

Test Symposium (ATS), 2010 19th IEEE Asian

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

19th IEEE Asian Test Symposium (ATS10)

Conference date

2010-12-01 - 2010-12-04

Conference place

Shanghai, China

Status

Published

ISBN/ISSN/Other

  • ISBN: 978-1-4244-8841-4