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An Architecture for Combined Test Data Compression and Abort-on-Fail Test

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Author

Summary, in English

The low throughput at IC (Integrated Circuit) testing is mainly due to the increasing test data volume, which leads to high ATE (Automatic Test Equipment) memory requirements and long test application times. In contrast to previous approaches that address either test data compression or abort-on-fail testing, we propose an architecture for combined test data compression and abort-on-fail testing. The architecture improves throughput through multi-site testing as the ATE memory requirement is constant and independent of the degree of multi-site testing. For flexibility in modifying the test data at any time, we make use of a test program for decompression; only test independent evaluation logic is added to the IC. Major advantages compared to MISR (Multiple-Input Signature Register) based schemes are that our scheme (1) allows abort-on-fail testing at clock-cycle granularity, (2) does not impact diagnostic capabilities, and (3) needs no special care for the handling of unknowns (X).

Publishing year

2007

Language

English

Pages

726-731

Publication/Series

[Host publication title missing]

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • testing
  • electronic systems
  • test data compression
  • unknowns

Conference name

Asia and South Pacific Design Automation Conference ASP-DAC '07

Conference date

2007-01-23 - 2007-01-26

Conference place

Yokohama, Japan

Status

Published

ISBN/ISSN/Other

  • ISBN: 1-4244-0629-3