A Digital PLL with a Multi-Delay Coarse-Fine TDC

Summary, in English

A 5GHz digital frequency synthesizer achieving a low noise for wireless RF application is presented. This architecture uses a multi-delay coarse-fine Time-to-Digital Converter (TDC) to achieve both the large detection range and fine resolution. A Digitally Controlled Oscillator (DCO) based on capacitive degeneration in LC-Tank is also implement-ed. The DCO achieves frequency quantization step of 300 Hz without any dithering. Simulated phase noise at 5 GHz carrier frequency is -125 and -151 dBc/Hz at 1 MHz and 20 MHz offset, respectively. The Digital phase-locked loop (DPLL) is realized in 90nm CMOS process and consumes 14mA from a 1.2V supply.

• Author: Ying Wu; Ping Lu; Pietro Andreani
• Department/s: Department of Electrical and Information Technology; ELLIIT: the Linköping-Lund initiative on IT and mobile communication
• Publishing year: 2011
• Language: English
• Publication/Series: [Host publication title missing]
• Links: http://dx.doi.org/10.1109/NORCHP.2011.6126745
• Document type: Conference paper
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: 29th Norchip conference, 2011
• Conference date: 2011-11-14 - 2011-11-15
• Conference place: Lund, Sweden
• Status: Published
• ISBN/ISSN/Other: ISBN: 978-1-4577-0514-4