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Single-electron transistors in heterostructure nanowires.

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Author

Summary, in English

Semiconductor-based single-electron transistors have been fabricated using heterostructure nanowire growth, by introducing a double barrier of InP into InAs nanowires. From electrical measurements, we observe a charging energy of 4 meV for the approximately 55 nm diameter and 100 nm long InAs islands between the InP barriers. The Coulomb blockade can be periodically lifted as a function of gate voltage for all devices, which is a typical signature of single-island transistors. Homogeneous InAs nanowires show no such effect for the corresponding voltage ranges. ©2003 American Institute of Physics.

Publishing year

2003

Language

English

Pages

2052-2054

Publication/Series

Applied Physics Letters

Volume

83

Issue

10

Document type

Journal article

Publisher

American Institute of Physics (AIP)

Topic

  • Chemical Sciences

Status

Published

Research group

  • Neuronano Research Center (NRC)

ISBN/ISSN/Other

  • ISSN: 0003-6951