Analysis and design of a low-power single-stage CMOS wireless receiver

Summary, in English

Abstract—The thorough analysis and the design of a complete

2.2 GHz quadrature receiver front-end suited for low-power

applications is reported in this work. The circuit, built in a 90nm

CMOS process, features a stacked single-ended low-noise amplifier

and a self-oscillating mixer. The oscillator LC tank is designed

to provide gain at low frequency without decreasing the quality

factor at the oscillating frequency. A careful analysis shows that

the parasitic capacitances at the output nodes ultimately limit

the achievable conversion gain.

Measurements show a conversion gain of 27.1 dB with a

14MHz bandwidth, a noise figure ranging from 12.4 to 13.2 dB

with a flicker corner frequency of 200 kHz and an input referred

1 dB compression point of -23.7 dBm. The circuit draws only

1.3mA from a 1.0V supply.

• Author: Matteo Camponeschi; Andrea Bevilacqua; Pietro Andreani
• Department/s: Department of Electrical and Information Technology
• Publishing year: 2009
• Language: English
• Pages: 1-4
• Publication/Series: [Host publication title missing]
• Links: http://dx.doi.org/10.1109/NORCHP.2009.5397826
• Document type: Conference paper
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: Norchip Conference, 2009
• Conference date: 2009-11-16 - 2009-11-17
• Conference place: Trondheim, Norway
• Status: Published
• Research group: Data converters & RF
• ISBN/ISSN/Other: ISBN: 978-1-4244-4310-9