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A 3.3v low-jitter frequency Synthesizer applied to fast Ethernet transceiver

Author

  • Ping Lu
  • Yan Wang
  • Lian Li
  • Junyan Ren

Summary, in English

A frequency synthesizer applied to a 10/100Base-T ethernet transceiver is described. It can work adaptively in either a 10Mbps or 100Mbps mode and convert freely from on mode to another. Cascode current sources and differential delay cells are adopted to guarantee good performance. The circuit meets the requirements of both transmitter on rising/falling time and receiver on CDR so that additional power and area are saved. Under some testing circumstance, rms jitter is only 22ps (with reference jitter of 25ps). The testing results prove that the frequency synthesizer has good processing stability and rejection to various noise. It works well for both transmitters and receivers. The circuit is designed with SMIC 0.35um standard CMOS technology and a power supply of 3.3v.

Publishing year

2005

Language

Chinese

Pages

1641-1645

Publication/Series

Journal of Semiconductors

Volume

26

Issue

8

Document type

Journal article

Publisher

IOS Press

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Ethernet frequency synthesizer clock jitter

Status

Published

ISBN/ISSN/Other

  • ISSN: 1674-4926