A mixed mode design flow for multi GHz ADPLLs
Author
Summary, in Swedish
Abstract in Undetermined
A systematic design approach for All Digital Phase Locked Loops (ADPLL) is presented. The whole system excluding Digitally Controlled Oscillator (DCO) and the Time to Digital Converter (TDC) can be synthesized easily in digital design flow. By using standard digital cells, no custom digital cells are needed. All the key problems in synthesis are solved well. The ADPLL is implemented in 90-nm CMOS process technology with the divider-by-two output clock of 2.7GHz. The current consumption is 6.5mA under the power supply of 1.2V.
A systematic design approach for All Digital Phase Locked Loops (ADPLL) is presented. The whole system excluding Digitally Controlled Oscillator (DCO) and the Time to Digital Converter (TDC) can be synthesized easily in digital design flow. By using standard digital cells, no custom digital cells are needed. All the key problems in synthesis are solved well. The ADPLL is implemented in 90-nm CMOS process technology with the divider-by-two output clock of 2.7GHz. The current consumption is 6.5mA under the power supply of 1.2V.
Department/s
Publishing year
2011
Language
English
Publication/Series
[Host publication title missing]
Document type
Conference paper
Publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
Keywords
- all digital phase locked loop
- current 2.5 mA
- digital cell
- digitally controlled oscillator
- divider-by-two output clock
- frequency 2.7 GHz
- mixed mode digital design flow
- multiGHz ADPLL
- size 90 nm
- systematic design approach
- time to digital converter
- voltage 1.2 V
- TDC
- DCO
- CMOS process technology
Conference name
29th Norchip conference, 2011
Conference date
2011-11-14 - 2011-11-15
Conference place
Lund, Sweden
Status
Published
Research group
- Analog RF
ISBN/ISSN/Other
- ISBN: 978-1-4577-0514-4