The browser you are using is not supported by this website. All versions of Internet Explorer are no longer supported, either by us or Microsoft (read more here: https://www.microsoft.com/en-us/microsoft-365/windows/end-of-ie-support).

Please use a modern browser to fully experience our website, such as the newest versions of Edge, Chrome, Firefox or Safari etc.

A VLSI architecture of the Schnorr-Euchner decoder for MIMO systems

Author

  • Zhan Guo
  • Peter Nilsson

Summary, in English

The lattice decoder is shown to approach the performance of Maximum-likelihood decoder for MIMO wireless systems with low complexity. A VLSI architecture of the K-best Schnorr-Euchner lattice decoder is proposed in this paper. The architecture is optimized on both algorithm and architecture levels, and supports a dynamic range of SNR [less-than or equal to] 30 dB. Compared to a conventional VLSI implementation of the lattice decoder for MIMO systems, the proposed architecture results in up to 37% computation reductions, 20% area savings and more than 5 times decoding throughput improvements. The proposed architecture is implemented with 0.35 μm technology for a system of 4 transmit/receive antennas and 16-QAM modulation. The results show that a decoding throughput of 53.3 Mbits/s can be achieved, and the decoding latency is less than 2.5 μs. © 2004 IEEE.

Publishing year

2004

Language

English

Pages

65-68

Publication/Series

Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication

Volume

1

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • MIMO
  • Packet error rates (PER)
  • Schnorr-Euchner decoder
  • Sphere decoders

Conference name

Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication

Conference date

2004-05-31 - 2004-06-02

Conference place

Shanghai, China

Status

Published

Research group

  • Elektronikkonstruktion

ISBN/ISSN/Other

  • ISBN: 0780379381