60 GHz Second Harmonic Power Amplifiers in 130-nm CMOS
Author
Summary, in English
Abstract—Two different frequency doubling power amplifiers have been measured, one with differential and one with single-ended input, both with single-ended output at 60 GHz. The amplifiers have been implemented in a 1p8M 130-nm CMOS process. The resonant nodes are tuned to 30 GHz or 60 GHz using on-chip transmission lines, which have been simulated in ADS and Momentum.
The measured input impedance of the single-ended PA is high at 250 Ω, and the differential input is similar, making the PA a suitable load for an oscillator in a fully integrated transmitter. The single-ended and differential input PA delivers 1 dBm and 3 dBm, respectively, of measured saturated output power to 50 Ω, both with a drain efficiency of 8%
The measured input impedance of the single-ended PA is high at 250 Ω, and the differential input is similar, making the PA a suitable load for an oscillator in a fully integrated transmitter. The single-ended and differential input PA delivers 1 dBm and 3 dBm, respectively, of measured saturated output power to 50 Ω, both with a drain efficiency of 8%
Publishing year
2008
Language
English
Pages
1-4
Publication/Series
Proceedings of Swedish System-on-Chip Conference (SSoCC)
Document type
Conference paper
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
Conference name
Swedish System-on-Chip Conference 2008 (SSoCC’08)
Conference date
2008-05-05 - 2008-05-06
Conference place
Gnesta, Sweden
Status
Published
Research group
- Analog RF