Buffer and Controller Minimization for Time-Constrained Testing of System-On-Chip
Author
Summary, in English
Publishing year
2003
Language
English
Pages
385-392
Publication/Series
[Host publication title missing]
Document type
Conference paper
Publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
Keywords
- test access mechanisms
- TAM
- system-on-chip
- SOC
- data transportation
- constraint logic programming
- test scheduling
Conference name
18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems DFT03
Conference date
2003-11-03 - 2003-11-05
Conference place
Boston, MA, United States
Status
Published
ISBN/ISSN/Other
- ISSN: 1550-5774
- ISBN: 0-7695-2042-1