Core-Level Expansion of Compressed Test Patterns

Summary, in English

The increasing test-data volumes needed for the testing of system-on-chip (SOC) integrated circuits lead to long test-application times and high tester memory requirements. Efficient test planning and test-data compression are therefore needed. We present an analysis to highlight the fact that the impact of a test-data compression technique on test time and compression ratio are method-dependant as well as TAM-width dependant. This implies that for a given set of compression schemes, there is no compression scheme that is the optimal with respect to test time reduction and test-data compression at all TAM widths. We therefore propose a technique where we integrate core wrapper design, test architecture design and test scheduling with test-data compression technique selection for each core in order to minimize the SOC test-application time and the test-data volume. Experimental results for several SOCs crafted from industrial cores demonstrate that the proposed method leads to significant reduction in test-data volume and test time.

• Author: Anders Larsson; Xin Zhang; Erik Larsson; Krishnendu Chakrabarty
• Publishing year: 2008
• Language: English
• Pages: 277-277
• Publication/Series: [Host publication title missing]
• Links: http://www.ida.liu.se/labs/eslab/publications/pap/db/anlar_ats08.pdf
• Document type: Conference paper
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Keywords: integrated circuits; system-on-chip; testing; test-data compression; memory requirements; wrapper design; test-application time
• Conference name: 17th Asian Test Symposium ATS
• Conference date: 0001-01-02
• Status: Published