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A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing

Author

Summary, in English

The increasingcost for System-on-Chip (SOC) testing is mainly due to the hugetest data volumes that lead to long test application time andrequire large automatic test equipment (ATE) memory. Testcompression and test sharing have been proposed to reduce the testdata volume, while test infrastructure and concurrent testscheduling have been developed to reduce the test application time.In this work we propose an integrated test scheduling and testinfrastructure design approach that utilizes both test compressionand test sharing as basic mechanisms to reduce test data volumes.In particular, we have developed a heuristic to minimize the testapplication time, considering different alternatives of testcompression and sharing, without violating a given ATE memoryconstraint. The results from the proposed Tabu Search basedheuristic have been validated using benchmark designs and arecompared with optimal solutions.

Publishing year

2007

Language

English

Pages

61-61

Publication/Series

[Host publication title missing]

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • testing
  • system-on-chip
  • memory reduction
  • test scheduling
  • test data compression
  • test sharing
  • tabu search

Conference name

IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 2007

Conference date

2007-04-11 - 2007-04-13

Conference place

Krakow, Poland

Status

Published

Research group

  • Digital ASIC

ISBN/ISSN/Other

  • ISBN: 1-4244-1162-9