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A Technique for Optimization of System-on-Chip Test Data Transportation

Author

Summary, in English

We propose a Tabu-search-based technique for time-constrained SOC (System-on-Chip) test data transportation. The technique makes use of the existing bus structure, where the advantage is, compared to adding dedicated test buses, that no additional routing is needed. In order to speed up the testing and to fulfill the time constraint, we introduce a buffer at each core, which in combination with dividing tests into smaller packages allows concurrent application of tests on a sequential bus. Our technique minimizes the combined cost of the added buffers and the test control logic. We have implemented the technique, and experimental results indicate that it produces high quality results at low computational cost.

Publishing year

2004

Language

English

Pages

179-180

Document type

Conference paper

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • system-on-chip
  • data transportation
  • test control logic

Conference name

9th IEEE European Test Symposium, 2004

Conference date

2004-05-23 - 2004-05-26

Conference place

Corsica, France

Status

Published