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Double-edge-triggered D-flip-flop for high speed CMOS circuits

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Author

  • Morteza Afgahi
  • Jiren Yuan

Summary, in English

Two circuits are proposed for double edge-triggered D flip-flops (DETDFFs). A DETDFF responds to both edges of the clock pulse. As compared with positive or negative edge-triggered flip-flops, a DETDFF has advantages in terms of power dissipation and speed. Delay figures for these circuits are measured by simulation. It is shown that these circuits are faster and have lower transistor counts than previously reported circuits. It is shown that these flip-flops can be used at 320-400-MHz clock frequency in a 2-μm technology.

Publishing year

1991

Language

English

Pages

1168-1170

Publication/Series

IEEE Journal of Solid-State Circuits

Volume

26

Issue

8

Document type

Journal article

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Status

Published

ISBN/ISSN/Other

  • ISSN: 0018-9200