The browser you are using is not supported by this website. All versions of Internet Explorer are no longer supported, either by us or Microsoft (read more here: https://www.microsoft.com/en-us/microsoft-365/windows/end-of-ie-support).

Please use a modern browser to fully experience our website, such as the newest versions of Edge, Chrome, Firefox or Safari etc.

A simulation model for embedding the transistor bias

På svenska

Author

  • Johan Piper
  • Jiren Yuan

Summary, in English

A simulation model for embedding the bias of a transistor is presented. The model exploits the simulator equilibrium point calculation to set the bias point of the transistor. The model uses negative feedback to set the bias point according to what the designer desires. When the simulator goes into its main analyses, the negative feedback is broken and embedded bias sources are added. This way it is possible to test an amplifier design before implementing the bias circuits. The model is technology independent and can be used on any kind of transistor

Publishing year

2004

Language

English

Pages

222-224

Publication/Series

[Host publication title missing]

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • negative feedback
  • amplifier design
  • transistor bias point simulation model
  • embedded bias sources
  • simulator equilibrium point calculation
  • transistor bias embedding

Conference name

22nd Norchip Conference, 2004

Conference date

2004-11-08 - 2004-11-09

Conference place

Oslo, Norway

Status

Published

ISBN/ISSN/Other

  • ISBN: 0-7803-8510-1