A low-power 8-bit folding A/D converter with improved accuracy

Summary, in English

In this paper, an accuracy improving method for calibration of mismatch-induced errors in folding A/D converter is presented. With dynamic auto-zero calibration for the folder, the transistor size of folding differential input pairs can be reduced considerably while keeping integral nonlinearity (INL) low. Using this technique, an 8-bit folding A/D converter is designed and simulated in MATLAB. Because of the calibration, conventional preamplifiers and offset averaging network before the folders are removed, saving a large power consumption and chip area. Results are demonstrated, showing the improved accuracy and the good agreement with the theoretical prediction

• Author: Cheng Chen; Jiren Yuan
• Department/s: Department of Electrical and Information Technology
• Publishing year: 2006
• Language: English
• Publication/Series: 2006 8th International Conference on Solid-State and Integrated Circuit Technology
• Links: http://dx.doi.org/10.1109/ICSICT.2006.306375
• Document type: Conference paper
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Keywords: analog-digital converter; folding A/D converter; folding differential input; dynamic auto-zero calibration; MATLAB; 8 bit; integral nonlinearity
• Conference name: 2006 8th International Conference on Solid-State and Integrated Circuit Technology
• Conference date: 2006-10-23 - 2006-10-26
• Conference place: Shanghai, China
• Status: Published
• ISBN/ISSN/Other: ISBN: 1-4244-0160-7