A 10-bit, 100-MHz CMOS linear interpolation DAC

Summary, in English

A 10-bit, 100-MHz CMOS linear interpolation digital-to-analog converter (DAC) is presented. It includes a 16-tap voltage controlled delay line and a 10-bit binary-weighted DAC with a time-interleaved structure. The linear interpolation not only increases the attenuation of the DAC's image components, but also reduces the glitch of the binary-weighted DAC. The requirement for the analog reconstruction filter is therefore greatly relaxed. The DAC is optimized for the single chip design of wire or wireless transmitters. The chip was fabricated in a standard 3.3 V, 0.35 μm, double-poly, triple-metal digital CMOS process. The core size of the chip is 0.49 mm × 0.52 mm, and power consumption is 86.5 mW with a 3.3 V power supply. The attenuation of image components is doubled (dB) compared with the conventional DAC

• Author: Zhou Yijun; Jiren Yuan
• Department/s: Department of Electrical and Information Technology
• Publishing year: 2002
• Language: English
• Pages: 471-474
• Publication/Series: ESSCIRC 2002. Proceedings of the 28th European Solid-State Circuit Conference
• Document type: Conference paper
• Publisher: Univ. Bologna
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Keywords: digital-to-analog converter; CMOS linear interpolation DAC; 16-tap voltage controlled delay line; binary-weighted DAC; time-interleaved structure; analog reconstruction filter; wire transmitters; wireless transmitters; digital CMOS process; double-poly triple-metal CMOS process; 10 bit; 100 MHz; 3.3 V; 0.35 micron; 86.5 mW
• Conference name: ESSCIRC 2002. Proceedings of the 28th European Solid-State Circuit Conference
• Conference date: 2002-09-24 - 2002-09-26
• Conference place: Firenze, Italy
• Status: Published
• ISBN/ISSN/Other: ISBN: 88-900847-9-0