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CMOS circuit speed optimization based on switch level simulation

På svenska

Author

  • Jiren Yuan
  • Christer Svensson

Summary, in English

The authors present a tool for transistor sizing for the purpose of speed optimization. The tool, called SLOP (switch-level optimization), is based on a switch-level simulation program for CMOS circuits. Consequently, the results are always verified by simulation. It gives the delay-area curve and the final sizes of each transistor according to the maximum width limitation specified by the user. Experimental results are presented. The typical improvement in circuit speed is 60%-90% with an area increase of 80%-110%.

Publishing year

1988

Language

English

Pages

2109-2112

Publication/Series

[Host publication title missing]

Volume

3

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

IEEE International Symposium on Circuits and Systems, 1988

Conference date

1988-06-07 - 1988-06-09

Conference place

Espoo, Finland

Status

Published