Realization of a floating-point A/D converter

Summary, in English

A floating-point analog-to-digital converter (FP-ADC) with a linear architecture has been implemented using an amplifier network in front of a pipeline ADC. The amplifier network has outputs with binary weighted gains, each sampled separately. The signal with the proper gain is then converted in the ADC. This structure allows instant floating point exponent determination. The mismatches in the amplifier network has been analyzed and successfully reduced. A prototype FP-ADC is currently being manufactured in a 0.35 μm double-poly CMOS process. Post-layout simulations show an operating frequency in excess of 30 MS/s with 74 dB dynamic range and 8 bit resolution.

• Author: Johan Piper; Jiren Yuan
• Department/s: Department of Electrical and Information Technology
• Publishing year: 2001
• Language: English
• Pages: 404-407
• Publication/Series: Proceedings of 2001 IEEE International Symposium on Circuits and Systems
• Volume: 1
• Links: http://dx.doi.org/10.1109/ISCAS.2001.921878
• Document type: Conference paper
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: IEEE International Symposium on Circuits and Systems, ISCAS, 2001
• Conference date: 2001-05-06 - 2001-05-09
• Conference place: Sydney, NSW, Australia
• Status: Published
• ISBN/ISSN/Other: ISBN: 0-7803-6685-9