A
Author
Summary, in English
This paper presents the hardware implementation
of a wavelet based event detector for cardiac pacemakers. A
high level energy estimation flow was applied to evaluate energy
efficiency of standard-cell based designs, over several CMOS
technology generations, from 180 to 65 nm, operated in the
sub-threshold domain. The simulation results indicate a 65 nm
low-leakage high-threshold (LL-HVT) CMOS technology as the favourable choice. Accordingly, the design was fabricated in 65 nm LL-HVT CMOS. Measurements validate the simulation results and prove that the circuit is fully functional down to a supply voltage of 250mV. At the energy minimum voltage of 320mV the circuit dissipates 0.88 pJ per sample at a clock rate
of 20 kHz.
of a wavelet based event detector for cardiac pacemakers. A
high level energy estimation flow was applied to evaluate energy
efficiency of standard-cell based designs, over several CMOS
technology generations, from 180 to 65 nm, operated in the
sub-threshold domain. The simulation results indicate a 65 nm
low-leakage high-threshold (LL-HVT) CMOS technology as the favourable choice. Accordingly, the design was fabricated in 65 nm LL-HVT CMOS. Measurements validate the simulation results and prove that the circuit is fully functional down to a supply voltage of 250mV. At the energy minimum voltage of 320mV the circuit dissipates 0.88 pJ per sample at a clock rate
of 20 kHz.
Department/s
Publishing year
2010
Language
English
Pages
253-258
Publication/Series
Proceedings of the 2010 18TH IEEE/IFIP International Conference on VLSI and System-on-Chip
Full text
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Document type
Conference paper
Publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
Conference name
18th IEEE/IFIP International Conference on VLSI and System-on-Chip
Conference date
2010-09-27 - 2010-09-29
Conference place
Madrid, Spain
Status
Published
Project
- Digital ASIC: Implementation of Signal Processing Algorithms for Pacemakers
Research group
- Elektronikkonstruktion
- Digital ASIC
ISBN/ISSN/Other
- ISBN: 978-1-4244-6469-2