Hardware architecture of IOTA pulse shaping filters for multicarrier systems

Summary, in English

This paper presents a hardware architecture of pulse shaping filter used in multicarrier systems. The filter can be configured to be used for both transmitter and receiver with limited overhead. Generic implementation complexity analysis for a filter in a multicarrier system with N sub-carriers is presented, while the implemented architecture is for a system with 128 sub-carriers. The pulse shaping filter is part of a larger system based on faster-than-Nyquist signaling and aided in an overall complexity reduction. Hence designing an efficient hardware architecture to keep the overhead moderate was the motivation behind this work. Architectural optimizations has been carried out in order to reduce area and power. The implementation of the proposed hardware architecture was carried out using a 65nm CMOS process. The chip core occupies an area of 0.11mm2 and is estimated to consume 14.4mW of power when running at

200MHz.

• Author: Shahid Mehmood; Deepak Dasalukunte; Viktor Öwall
• Department/s: Department of Electrical and Information Technology; ELLIIT: the Linköping-Lund initiative on IT and mobile communication
• Publishing year: 2013
• Language: English
• Pages: 733-742
• Publication/Series: IEEE Transactions on Circuits and Systems Part 1: Regular Papers
• Volume: 60
• Issue: 3
• Links: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6316099&contentType=Early+Access+Articles&ranges%3D2011_2012_p_Publication_Year%26queryText%3Ddasalukunte; http://dx.doi.org/10.1109/TCSI.2012.2215749
• Document type: Journal article
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Status: Published
• Project: EIT_SOS VINNOVA Industrial Excellence Center - System Design on Silicon
• Research group: Elektronikkonstruktion
• ISBN/ISSN/Other: ISSN: 1549-8328