CMOS Analog-to-Digital Converters - Analysis, Modeling, and Design
Author
Summary, in English
A high-performance and flexible analog-to-digital converter (ADC), that can be integrated in deep-submicron CMOS technology, is a key building block for reduced size, cost and power consumption of digital communication systems. This dissertation concerns the investigation of particular problems associated with the design of such ADCs.
The problem of increased clock jitter sensitivity of low-pass (LP), 1-bit, continuous-time (CT) Delta-Sigma modulators with return-to-zero (RZ) feedback is studied. A high-level behavioral model is developed that can be used to simulate the dominant clock phase noise effects, with arbitrary clock phase noise and input signals, quickly and accurately. The accuracy of the presented model is verified by measurements on a second order LP CT Delta-Sigma modulator circuit with switched current (SI) RZ feedback digital-to-analog converter (DAC). As part of the verification a simulation and measurement technique is developed that enables studies of the clock phase noise sensitivity for different frequency offsets separately. It is found by simulations that the wide-band clock phase noise, modulating the amount of charge delivered, per clock period, by the traditional SI (RZ) feedback DAC, is the dominating effect in many practical situations. To reduce the sensitivity to wide-band clock phase noise, a switched-capacitor switched-resistor (SCSR) feedback DAC concept is proposed, which makes the amount of charge per clock period less dependent on the exact timing of the clock edges. The architecture has the additional benefit of reducing the typically high SC DAC output peak currents, resulting in reduced slew-rate requirements for the loop-filter integrator(s). A functional level analysis of the trade-offs between the reduction of the pulse-width jitter sensitivity, the DAC output peak current and the SC discharge time constant is carried out. To demonstrate the concept and to verify the reduced pulse-width jitter sensitivity a 5-mW, 312-MHz, second order, LP, 1-bit, CT Delta-Sigma modulator with SCSR feedback has been implemented in a 1.2-V 90-nm RF-CMOS process. A signal-to-noise ratio (SNR) of 66.4dB and a signal-to-noise-and-distortion-ratio (SNDR) of 62.4dB is measured in a 1.92MHz bandwidth. The measurements show that the sensitivity to wide-band clock phase noise is reduced by 30dB compared to a traditional SI (RZ) DAC.
Additionally, the problems with offset and gain mismatch between the ADC units in a randomly time-interleaved successive-approximation (SA) ADC system is studied by measurements of a 12-bit, 30-MSPS, randomly time-interleaved SA-ADC circuit. The effectiveness of previously presented error estimation and equalization algorithms is verified using the measured data, through an SNDR improvement of more than 10dB after error equalization.
Moreover, a sampling rate and resolution reconfigurable pipeline/cyclic ADC is proposed. Circuit techniques developed to enable the reconfiguration is presented. A 10-bit 80-MSPS pipeline/cyclic ADC, with 8 configurations, has been implemented in a 0.18-um CMOS process. The ADC performance is verified by measurements.
The problem of increased clock jitter sensitivity of low-pass (LP), 1-bit, continuous-time (CT) Delta-Sigma modulators with return-to-zero (RZ) feedback is studied. A high-level behavioral model is developed that can be used to simulate the dominant clock phase noise effects, with arbitrary clock phase noise and input signals, quickly and accurately. The accuracy of the presented model is verified by measurements on a second order LP CT Delta-Sigma modulator circuit with switched current (SI) RZ feedback digital-to-analog converter (DAC). As part of the verification a simulation and measurement technique is developed that enables studies of the clock phase noise sensitivity for different frequency offsets separately. It is found by simulations that the wide-band clock phase noise, modulating the amount of charge delivered, per clock period, by the traditional SI (RZ) feedback DAC, is the dominating effect in many practical situations. To reduce the sensitivity to wide-band clock phase noise, a switched-capacitor switched-resistor (SCSR) feedback DAC concept is proposed, which makes the amount of charge per clock period less dependent on the exact timing of the clock edges. The architecture has the additional benefit of reducing the typically high SC DAC output peak currents, resulting in reduced slew-rate requirements for the loop-filter integrator(s). A functional level analysis of the trade-offs between the reduction of the pulse-width jitter sensitivity, the DAC output peak current and the SC discharge time constant is carried out. To demonstrate the concept and to verify the reduced pulse-width jitter sensitivity a 5-mW, 312-MHz, second order, LP, 1-bit, CT Delta-Sigma modulator with SCSR feedback has been implemented in a 1.2-V 90-nm RF-CMOS process. A signal-to-noise ratio (SNR) of 66.4dB and a signal-to-noise-and-distortion-ratio (SNDR) of 62.4dB is measured in a 1.92MHz bandwidth. The measurements show that the sensitivity to wide-band clock phase noise is reduced by 30dB compared to a traditional SI (RZ) DAC.
Additionally, the problems with offset and gain mismatch between the ADC units in a randomly time-interleaved successive-approximation (SA) ADC system is studied by measurements of a 12-bit, 30-MSPS, randomly time-interleaved SA-ADC circuit. The effectiveness of previously presented error estimation and equalization algorithms is verified using the measured data, through an SNDR improvement of more than 10dB after error equalization.
Moreover, a sampling rate and resolution reconfigurable pipeline/cyclic ADC is proposed. Circuit techniques developed to enable the reconfiguration is presented. A 10-bit 80-MSPS pipeline/cyclic ADC, with 8 configurations, has been implemented in a 0.18-um CMOS process. The ADC performance is verified by measurements.
Publishing year
2008
Language
English
Full text
Document type
Dissertation
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
Status
Published
Research group
- Data converters & RF
Supervisor
- Jiren Yuan
Defence date
5 June 2008
Defence time
13:15
Defence place
Room E:1406, E-building, Ole Römers väg 3, Lund university, Faculty of Engineering
Opponent
- Franco Maloberti (Prof.)