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Energy dissipation reduction of a cardiac event detector in the sub-Vt domain by architectural folding

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Author

Summary, in English

This manuscript presents the digital hardware realization of a wavelet based event detector for cardiac pacemaker applications. The architecture of the detector is partially folded to minimize hardware cost. An energy model is applied to evaluate the energy efficiency the sub-threshold (sub-VT ) domain. The design is synthesized in 65nm low leakage-high threshold CMOS technology, and it is shown that folding reduces the area cost by 30.6 %. Folding decreases energy dissipation of the circuit by 14.4% in the sub-VT regime, where the circuit dissipates 3.3 pJ per sample at VDD=0.26 V.

Publishing year

2010

Language

English

Pages

347-356

Publication/Series

Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation

Volume

5953

Document type

Conference paper

Publisher

Springer

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • folding
  • energy model
  • sub-threshold
  • QRS detection
  • Cardiac pacemaker
  • wavelet filterbank
  • time-multiplexing

Conference name

19th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2009

Conference date

2009-09-09 - 2009-09-11

Conference place

Netherlands

Status

Published

Project

  • Digital ASIC: Implementation of Signal Processing Algorithms for Pacemakers

Research group

  • Elektronikkonstruktion
  • Digital ASIC

ISBN/ISSN/Other

  • ISSN: 1611-3349
  • ISSN: 0302-9743