The browser you are using is not supported by this website. All versions of Internet Explorer are no longer supported, either by us or Microsoft (read more here: https://www.microsoft.com/en-us/microsoft-365/windows/end-of-ie-support).

Please use a modern browser to fully experience our website, such as the newest versions of Edge, Chrome, Firefox or Safari etc.

A sign-bit auto-correlation architecture for fractional frequency offset estimation in OFDM

Author

Summary, in English

This paper presents an architecture of an auto-correlator for Orthogonal Frequency Division Multiplexing systems. The received signal is quantized to only the sign-bit, which dramatically simplifies the frequency offset estimation. Hardware cost is reduced under the assumption that synchronization during acquisition does not have to be very accurate, but sufficient for coarse estimation. The architecture is synthesized towards a 65nm low-leakage high threshold standard cell CMOS library. The proposed architecture results in area reduction of 93% if compared to typical 8-bit implementation. The area occupied by the architecture is 0.063mm^2. The architecture is evaluated for WLAN, LTE and DVB-H. Power simulations for DVB-H transmission shows a power consumption of 4.8uW per symbol.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • frequency offset
  • DVB-H
  • WLAN
  • Sign-Bit
  • OFDM
  • LTE

Conference name

IEEE International Symposium on Circuits and Systems (ISCAS), 2010

Conference date

2010-05-30 - 2010-06-02

Conference place

Paris, France

Status

Published

Project

  • Radiosystem: Multibase (EU, VÖ/OE)

Research group

  • Elektronikkonstruktion
  • Digital ASIC