The browser you are using is not supported by this website. All versions of Internet Explorer are no longer supported, either by us or Microsoft (read more here: https://www.microsoft.com/en-us/microsoft-365/windows/end-of-ie-support).

Please use a modern browser to fully experience our website, such as the newest versions of Edge, Chrome, Firefox or Safari etc.

Extended STAPL as SJTAG Engine

På svenska

Author

Summary, in English

Integrated Circuits (ICs) and multi-board systems are becoming increasingly complex to test. A key to successful testing is effective standards. Currently, at micro level the Internal JTAG (IJTAG) focuses on the development of a standard for embedded on-chip instruments while at macro level the System JTAG (SJTAG) works on defining a standard for system level test management; mainly connecting the IJTAG standard with the system test manager. In this paper we discuss language requirement for making and handling access between the test manager and embedded instruments. As a base-line we make use of the Standard Test and Programming Language (STAPL). We have identified a number of required extensions that we have implemented in an extended STAPL++ player (interpreter) and language. We have performed initial experiments where we simulated an embedded environment with a PC as test controller running the new player and an FPGA serving as device-under-test.

Publishing year

2007

Language

English

Pages

119-119

Publication/Series

[Host publication title missing]

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • testing
  • multi-board systems
  • language requirement
  • test protocol
  • standards

Conference name

European Test Symposium, 2007

Conference date

2007-11-20 - 2007-11-24

Conference place

Freiburg, Germany

Status

Published

Research group

  • Digital ASIC