Vertical III-V Nanowire Tunnel Field-Effect Transistors : A Circuit Perspective
Author
Summary, in English
The energy scaling of integrated circuits has reached its limit because the operating voltage of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFET) based switches has reached its minimum value. MOSFETs are limited by thermionic emission and cannot achieve a subthreshold swing (SS) below 60 mV/decade at room temperature. Tunnel Field-Effect Transistors (TFET), which operate on field modulation of band-to-band tunneling (BTBT), can deliver SS less than 60 mV/dec and are considered as a potential alternative for MOSFETs to further scale down the supply voltage.
This thesis work studied the capabilities and limitations of n-type TFETs based on III-V vertical nanowires and their circuit implementation. TFETs were fabricated using vertical InAs/GaSb or InAs/InGaAsSb/GaSb nanowires of high material
quality, and, switching from InAs/GaSb to InAs/InGaAsSb/GaSb allowed for optimization of the heterojunction, resulted in improvement of the device metrics. Along with heterostructure optimization, the dopant introduction and concentration were systematically varied to achieve devices with record performance. These devices achieved a minimum subthreshold swing of 42 mV/dec and a record high I60 of 1.2 μA/μm at a drive voltage of 0.5 V. The stability and high yield of the process allowed for statistical study of correlations between important device parameters such as I60, on-current, subthreshold swing, and off-current. The implementation of circuits was also aided by sufficient process repeatability and yield.
To implement circuits based on these TFETs, the fabrication process was optimized with introduction of mesa and nonorganic spacers. Voltage based circuits in the following configurations were implemented: a current mirror, a diode connected inverter and a cascode buffer. Individual TFETs in the circuit operate well below 60 mV/dec operation with minimum achieved subthreshold swing (SS) of 30 mV/dec at drain voltage of 400 mV. In circuit operation, individual devices were connected via FEOL and are biased at 300 mV supply voltage, with an input frequency of 200 kHz. To explore current-mode based design principle, a current conveyor circuit was implemented, which exhibits large-signal voltage gain of 0.89 mV/mV, a current gain of 1 nA/nA and an operating frequency of 320 kHz.
Additionally, self-heating in a vertical nanowire device was examined using pulsed IV methodology. The results indicate that the intrinsic temperature rises to 385 K when the device is operated in DC at room temperature (300 K) with a thermal time constant of 1 μs. We find that self-heating is a limiting factor for device performance.
This thesis work studied the capabilities and limitations of n-type TFETs based on III-V vertical nanowires and their circuit implementation. TFETs were fabricated using vertical InAs/GaSb or InAs/InGaAsSb/GaSb nanowires of high material
quality, and, switching from InAs/GaSb to InAs/InGaAsSb/GaSb allowed for optimization of the heterojunction, resulted in improvement of the device metrics. Along with heterostructure optimization, the dopant introduction and concentration were systematically varied to achieve devices with record performance. These devices achieved a minimum subthreshold swing of 42 mV/dec and a record high I60 of 1.2 μA/μm at a drive voltage of 0.5 V. The stability and high yield of the process allowed for statistical study of correlations between important device parameters such as I60, on-current, subthreshold swing, and off-current. The implementation of circuits was also aided by sufficient process repeatability and yield.
To implement circuits based on these TFETs, the fabrication process was optimized with introduction of mesa and nonorganic spacers. Voltage based circuits in the following configurations were implemented: a current mirror, a diode connected inverter and a cascode buffer. Individual TFETs in the circuit operate well below 60 mV/dec operation with minimum achieved subthreshold swing (SS) of 30 mV/dec at drain voltage of 400 mV. In circuit operation, individual devices were connected via FEOL and are biased at 300 mV supply voltage, with an input frequency of 200 kHz. To explore current-mode based design principle, a current conveyor circuit was implemented, which exhibits large-signal voltage gain of 0.89 mV/mV, a current gain of 1 nA/nA and an operating frequency of 320 kHz.
Additionally, self-heating in a vertical nanowire device was examined using pulsed IV methodology. The results indicate that the intrinsic temperature rises to 385 K when the device is operated in DC at room temperature (300 K) with a thermal time constant of 1 μs. We find that self-heating is a limiting factor for device performance.
Publishing year
2023
Language
English
Document type
Dissertation
Publisher
Electrical and Information Technology, Lund University
Topic
- Other Electrical Engineering, Electronic Engineering, Information Engineering
Keywords
- Low-Power Electronics
- Self-Heating
- Steep Slope Devices
- Tunnel Field-Effect Transistors
- Vertical Nanowire
- III-V Semiconductors
Status
Published
Research group
- Nano Electronics
ISBN/ISSN/Other
- ISBN: 978-91-8039-887-9
- ISBN: 978-91-8039-886-2
Defence date
15 December 2023
Defence time
09:15
Defence place
Lecture Hall E:B, building E, Ole Römers väg 3, Faculty of Engineering LTH, Lund University, Lund. The dissertation will be live streamed, but part of the premises is to be excluded from the live stream.
Opponent
- Frances Balestra (Dr.)