Energy-Efficient Redundant Execution for Chip Multiprocessors

Summary, in English

Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chip fault tolerance in future chip microprocessors (CMPs). In this paper, we describe a power-efficient architecture for redundant execution on chip multiprocessors (CMPs) which when coupled with our per-core dynamic voltage and frequency scaling (DVFS) algorithm significantly reduces the energy overhead of redundant execution without sacrificing performance. Our evaluation shows that this architecture has a performance overhead of only 0.3% and consumes only 1.48 times the energy of a non-fault-tolerant baseline.

• Author: Pramod Subramanyan; Virendra Singh; Kewal K. Saluja; Erik Larsson
• Publishing year: 2010
• Language: English
• Pages: 143-146
• Publication/Series: Proceedings of the 20th symposium on Great lakes symposium on VLSI
• Links: http://dx.doi.org/10.1145/1785481.1785516
• Document type: Conference paper
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: Great Lakes Symposium on VLSI (GLSVLSI'10), 2010
• Conference date: 2010-05-16 - 2010-05-18
• Conference place: Providence, United States
• Status: Published
• ISBN/ISSN/Other: ISBN: 978-1-4503-0012-4