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Survivor path processing in Viterbi decoders using register exchange and traceforward

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Author

Summary, in English

This paper proposes a new class of hybrid VLSI

architectures for survivor path processing to be used in Viterbi decoders. The architecture combines the benefits of register exchange and trace-forward algorithms, that is, low memory requirement and latency versus implementation efficiency. Based on a structural comparison, it becomes evident that the architecture

can be efficiently applied to codes with a larger number

of states where usually trace-back-based architectures, which increase latency, are dominant.

Publishing year

2007

Language

English

Pages

537-541

Publication/Series

IEEE Transactions on Circuits and Systems II: Express Briefs

Volume

54

Issue

6

Document type

Journal article

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • (TB)
  • traceback
  • survivor path
  • convolutional codes
  • register exchange (RE)
  • traceforward (TF)
  • Viterbi decoder
  • VLSI

Status

Published

Project

  • Digital ASIC: Flexible Coding and Decoding for Wireless Personal Area Networks

ISBN/ISSN/Other

  • ISSN: 1549-7747