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The Design and Optimization of SOC Test Solutions

På svenska

Author

Summary, in English

We propose an integrated technique for extensive optimization of the final test solution for System-on-Chip using Simulated Annealing. The produced results from the technique are a minimized test schedule fulfilling test conflicts under test power constraints and an optimized design of the test access mechanism. We have implemented the proposed algorithm and performed experiments with several benchmarks and industrial designs to show the usefulness and efficiency of our technique.

Publishing year

2001

Language

English

Pages

523-530

Publication/Series

[Host publication title missing]

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • system-on-chip
  • testing
  • test conflicts
  • optimized design
  • embedded systems

Conference name

IEEE/ACM International Conference on Computer Aided Design, ICCAD 2001

Conference date

2001-11-04 - 2001-11-08

Conference place

San Jose, CA, United States

Status

Published

ISBN/ISSN/Other

  • ISSN: 1092-3152
  • ISBN: 0-7803-7247-6